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rev. 1.1 7/11 copyright ? 2011 by silicon laboratories si3050-evb si3050-evb si3050 e valuation b oards : si3050ppt-evb, si3050ppt1-evb, SI3050FMPPT-EVB description the si3050 evaluation boards provide the telecommunications system engineer an easy way to evaluate the functionality of silicon laboratories? si3050/si3019 or si3050/3018 integrated voice direct access arrangement (daa) solutions. the si3050 integrates an spi, pcm, and gc i serial interface as well as system-side daa functionality. in conjunction with the si3019 or si3018 global line-side silicon daa chip, it provides a low-cost, solid -state, globally-compliant voice daa solution. there are three different si3050 evaluation boards available: ? the si3050ppt-evb allows evaluation of the si3050 and si3019 devices in tssop packages. ? the si3050ppt1-evb allows evaluation of the si3050 and si3018 devices in tssop packages. ? the SI3050FMPPT-EVB allo ws evaluation of the si3050 and si3019 devices in qfn packages. the si3050 evaluation boards can be easily controlled from a pc using the supplied application software. features ? ability to read and write daa registers ? dac waveform generation from a series of standard waveforms or fr om a .wav file ? adc data capture and display in either time or frequency domain ? recommended layout for key components ? daisy-chain support functional block diagram si3050 ppt bom tip ring bnc/audio precision box si3019 spi pcm/gci fpga si-link daughter card optional ground start circuit optional speaker
si3050-evb 2 rev. 1.1 1. functional description the si3050 evaluation boards provide the telecommunications system engineer an easy way to evaluate the si3050 plus si3018/3019 solution. silicon labs? daas are integrated direct access arrangements that provide a digital, low-cost, solid-sate interface to worldwide telephone lines. through the patented isocap? technology, these chipsets eliminate the need for an analog frond end (afe), an isolation transformer, relays, opto-isolators, an d a 2- to 4-wire hybrid. the si3050 evaluation boards also support the connection of multiple devices on an spi/pcm interface. the evaluati on boards provide a straightforward means of evaluating this feature. the evaluation board c onsists of the si-link motherboard and one of the three available si3050 daughter cards. a custom ribbon cable is also provided to connect to the parallel port of a pc. contact a silicon laboratories representative for more information. 1.1. motherboard-daughter card connec- tion the si3050 daughter card connects to the si-link motherboard through five sockets, js1?js5. js1 is a 5x2 socket and js2 is a 2x2 socket connecting spi digital signals of the si3050. js3 is a 5x2 socket connection reserved for future use. js4 is a 5x2 socket connection that routes the vdd regulated supply. js5 is a 5x2 socket connection to the pcm digital signals of the si3050. js3 is a no-connect in this application. 1.2. power supply power is supplied to the si-link motherboard by means of j1 and j4. j4 is a 2.1 mm power jack that allows the use of a wall transformer. a 9 v supply/ 300 ma is typically used, but the on-board voltage regulator will also work with a dc voltage between 7.5 v and 20 v. a diode bridge is used to correct polarity. the on-board regulator, u7, provides 5 v to the call progress circuit, the on-board oscilla tor, and other boards daisy chained to the motherboard. this 5 v is further regulated to 3.3 v to power the daughter card and the input/output ports of the motherboard's fpga. a third regulator provides 2.5 v for the core voltage of the fpga. j1 is a no-connect in this application. 1.3. clock generation the si3050 requires an fsync, pclk, and sclk input. an on-board oscillator (y1) is used by the fpga to clock all the subsystems as well as generate and provide the fsync, pclk, and sclk to the daa. fpga is designed to use a 32.768 mhz oscillator (included with the board). 1.4. reset circuit the si3050 chipset requires an active low pulse on reset following power up and whenever all registers need to be reset. for development purposes, the si- link motherboard includes a reset push button, sw1, that is used by the fpga to generate a reset pulse of the daa. 1.5. line connection j1 is provided to connect the si3050 daughter board to a standard rj-11 connector. the system cannot execute an off-hook command without the phone line connected. 1.6. pc parallel port jp2 and p3 connect through the silicon labs custom ribbon cable to the parallel port of the pc. the parallel port connection allows the designer to read and write the daa registers using the evaluation software included with the evaluation board.
si3050-evb rev. 1.1 3 2. configuring the si-link the si-link motherboard is used to interface the si3050 to a pc or other audio system for easy evaluation. it uses an fpga to translate the parallel port interface to either spi/pcm, spi-only, or gci to communicate with the si3050. when in spi/pcm mode, the pcm audio data and spi control data are communicated from the controlling pc using the aforementioned software. this mode allows the user to evaluate the daa without any lab equipment other than a pc. by selecting spi-only operation, the pc is still used to control the daa through the spi bus, but the pcm audio data is routed from an external source. this external source may be an audio precision system using the p1 and p2 headers or a pcm highway using the bnc connectors, j5?j8 (not populated). to evaluate the si3050?s operation with the gci interface, the pc may be used to send the audio data and control. the fpga performs the necessary translation to communicate to the si3050 in this mode. the fourth mode of operation is the pass-thru mode. in this mode, the fpga is only used to route the gci bus to the audio precision or bnc headers on the si-link board. in this mode, a pc is not required to control the evaluation platform. 3. configuring the si3050dc-evb the si3050dc-evb has six ju mpers. the first five control the boot-strap options for configuring the si3050. the default state is set to allow the si3050 to be controlled using the spi bus. see figure 1. figure 1. spi control mode default state by changing the jumper configuration prior to powering the board, the mode of the board can be set according to tables 1?3. jp10 is the sixth jumper on the si-link motherboard. moving this jumper to the int position routes pin 9 of the si3050 to the si-link motherboard. when the jumper is in the aout positi on, this signal is routed to the optional call progress speaker system, which is not populated by default on the evaluation platform. refer to the aout pwm circuit in the si3050 data sheet for values used to populate this circuit. mode jp3 (source) jp4 (format) spi/pcm 0 0 spi-only 1 0 gci 0 1 pass-thru 1 1 0 sclk 1 0 sdi_thru 1 0cs 1 0 sdo 1 0 sdi 1 table 1. pcm or gci highway mode selection sclk sdi mode selected 1 x pcm mode 0 0 gci mode, b2 channel used 0 1 gci mode, b1 channel used note: values shown are the states of the pins at the rising edge of reset. table 2. pin functionality in pcm or gci highway mode pin name pcm mode gci mode sdi_thru spi data through- put pin for daisy chaining operation (connects to the sdi pin of the subse- quent device in the daisy chain) sub-frame selector, bit 2 sclk spi clock input pcm/gci mode selector sdi spi serial data input b1/b2 channel selector sdo spi serial data out- put sub-frame selector, bit 1 cs spi chip select sub-frame selector, bit 0 fsync pcm frame sync input gci frame sync input pclk pcm input clock gci input clock dtx pcm data transmit gci data transmit drx pcm data receive gci data receive note: this table denotes pin functionality after the rising edge of reset and mode selection.
si3050-evb 4 rev. 1.1 table 3. gci mode sub-frame selection sdi_thru sdo cs gci subframe 0 selected (voice channels 1?2) 111 gci subframe 1 selected (voice channels 3?4) 110 gci subframe 2 selected (voice channels 5?6) 101 gci subframe 3 selected (voice channels 7?8) 100 gci subframe 4 selected (voice channels 9?10) 011 gci subframe 5 selected (voice channels 11?12) 010 gci subframe 6 selected (voice channels 13?14) 001 gci subframe 7 selected (voice channels 15?16) 000
si3050-evb rev. 1.1 5 4. evaluation software the si3050 evaluation boards include an easy-to-use graphical interface for controlling the evaluation platform. this software a llows the system designer to characterize the si3050 daa performance without constructing any custom hardware. the evaluation software includes th e following features: ? ability to read and write daa registers using the spi or gci bus ? dac waveform generation from a series of standard waveforms or from a .wav file ? adc data capture and display in either the time or frequency domain using either pcm or gci bus ? daisy-chain support ? transmit and receive path attenuation and gain settings ? ring detection ? loop current measurement 4.1. pc system requirements the application software for the si3050 evaluation boards has the following system requirements: ? windows98 ? , windows2000 ? , or windowsxp ? ? available parallel port ?? epp or ecp parallel port mode for windows 98 ? ?? epp parallel port mode for windows 2000 ? and windowsxp ? ? 450 mhz pentium ii ? or greater recommended ? 64 mb of memory or greater recommended 4.2. installation the supplied cd co ntains the si3050ppt-evb windows driver files as well as a setup utility for installing the evaluation software. to install the si3050ppt-evb software, run the installation program on the ?silicon laboratories wireline software cd.? the path for the installation program is si3050 evaluation software\setup.exe. the installer guides the user through the installation process for si3050ppt-evb.exe and the labview run-time engine. 5. using the si3050ppt-evb application software a shortcut for starting the application software that controls the evaluation board is installed in the windows start menu under the programs folder in the ?si3050 evaluation software? folder. 5.1. application menus three pulldown menus are used to configure the operation of the software: ? run : ?? exit: stops the program ?? save: stores the audio waveform into .wav files ? configure : ?? configure daa: display hardware status and user configuration. user can set advanced software options. ?? reset daa: resets daa and executes basic initialization sequences on reg 1, reg 5?7, reg 33?37, and reg 42 ? design tool ?? register map: displays register map of si3050 ?? signal flow diagram: displays signal flow diagram of si3050 and si3019. ?? transhybrid loss calculation: calculate transhybrid loss over frequency ?? ringing: help user program ring validation registers. ? help : displays information about the evaluation board
si3050-evb 6 rev. 1.1 figure 2. si3050ppt-evb evaluation soft ware in the dsp mode control and rcv source control view 5.2. dsp mode and rcv source control view the user interface in the dsp mode and rcv source control view for the si3050 ppt_evb software is shown in figure 2. this figure shows the daa?s mode of communication and rcv source for each channel when the application is launched. dsp mode control dsp mode control is descr ibed in the following list: ? format : selects the format of the audio data to be transmitted over pcm or gci bus. by changing the format, the software will automatically execute a write to daa register 33 pcmf bits or daa register 44 gcif bits. ? daa interface mode : selects the mode of operation of the daa from spi/pcm, spi/bnc, gci, or gci/ bnc. upon startup, this mode will reflect the ?format? and ?source? jumper selection on the silink (mother) board. the selection made via the jumper can be overwritten here. ? pcm clock mode : selects the clock mode of pcm from 1x to 2x. ? pclk frequency : selects the frequency of the pclk in pcm mode from 256 khz to 8.192 mhz in power of 2. ? sclk frequency : selects the frequency of the sclk from 256 khz to 8.192 mhz in power of 2. ? spi mode : selects the length of cs to either 8-bit or 16-bit. ? gci clock mode : selects the frequency and clock mode of pclk in gci mode from either 1x 2.048 mhz or 2x 4.096 mhz. ? gci subframe : selects the subframe in gci mode with which to communicate. ? b-channel : selects the b channel desired during gci communication. changes in the dsp mode pane l will not take effect until assertion of the ?reset & reinitialize the system? button. 5.2.1. rcv source control rcv source control utilizes the daisy-chain capability of the daa in spi/pcm communication mode. rcv source determines the source of audio data for each device on the silink board. changes in rcv source will not take effect until assertion of the ?update rcv source? button.
si3050-evb rev. 1.1 7 figure 3. si3050ppt-evb eval uation software in the audio data monitoring view 5.3. audio data monitoring view the audio data monitoring view is discussed in the following sections. 5.3.1. receive audio data of channel# allows selection of channel to control and view. the audio data monitoring view allows the generation of dac data and the capture and display of adc data. operation of the front panel in line monitoring view is detailed in the following list. see figure 3. 5.3.2. tx control ? dac waveform : selects the waveform to be generated by the dac. the waveform types are as follows: dc, sine, square , ramp, and .wav file. ? tx gain (db) : selects the transmit path gain/ attenuation. ? tx mute: mutes the transmit path ? amplitude : sets the amplitude of the dac waveform in either volts or the units of dac codes. the units are determined by the amplitude units control. ? frequency : selects the frequency (hz) of the waveform to generate. the actual waveform frequency may vary slightly from the entered value. this variation is due to the requiremen t to fit an integer number of samples into the transmit buffer. the control is updated to reflect the actual waveform frequency generated. the equation for calculating the frequency of the wa veform is as follows: actual frequency = round ((waveform frequency/dac sample rate) x buffersize ) x (dac sample rate/ buffersize)
si3050-evb 8 rev. 1.1 5.3.3. rx control ? monitor mode : allows the selection of several data modes. digital loopback mode routes the dac data back to the receive path. on-hook mode configures the daa to the on-hook mode. off-hook mode configures the daa to the off-hook mode. on-hook line monitoring mode configures the daa to the line monitoring state. ? rx gain (db): selects the receive path gain/ attenuation. ? rx mute: mutes the receive path ? ring detect mode: allows selection of full-wave or half-wave ring detection. 5.3.4. dialer ? dial number: inputs dial number ? dial: executes dial 5.3.5. measurement ? loop current : displays the loop current when in off- hook mode. ? ring detect bits : displays the state of the ring detect bits when in on-hook mode. ? off-hook : indicates that the daa is in the off-hook state. ? dc level/sinad : displays either the dc level of the time domain waveform or the sinad of the frequency doma in waveform. ? rms level/frequency : displays either the rms level of the time domain waveform or the frequency of the largest peak in the frequency domain waveform. ? num avg for fft : when in fft display, the software will automatically average waveforms. this panel selects the number of averages to take. 5.3.6. wave display controls ? display type : selects how the adc data is displayed on the waveform graph (time or frequency domain). ? amplitude units : sets the amplitude units for the waveform graph and amplitude control to either volts or codes. ? acquisition : used to run or pause the codec data stream. upon pausing the acquisition of the data, it displays measurement values regardless of the status of ?display measur ement? under the configure menu. ? x autoscale : automatically scales the x-axis of the graph to fit the entire waveform. ? y autoscale : automatically scales the y-axis to fit the entire vertical range of the waveform. ? xmin : sets the origin of the x-axis when x autoscale is disabled. ? x zoom : used to zoom a portion of the displayed waveform when x autosca le is disabled. the waveform starts at xmin and 1/x zoom of the total waveform is displayed. ? yo : sets the origin of the y-axis when y autoscale is disabled. half of the waveform is displayed above yo, and half is displayed below yo.
si3050-evb rev. 1.1 9 figure 4. si3050ppt-evb evaluation software in the register table display view 5.4. register table display view the daa register view allows the si3050 daa registers to be read or written. the user interface for the daa register view is shown in figure 4. operation of the front panel in the daa register view is detailed in the following list: ? table : this table displays the contents of the si3050 daa registers in realtime. ? daa reg num : the si3050 daa register number to write (in decimal). ? daa reg value : the contents to write to the register selected by the daa reg num control (in hexadecimal). ? write daa regs : causes the contents of the daa reg value control to be wr itten to the daa reg num register. ? broadcast : turns on the broadcast bit (spi only). ? fdt : shows the status of fdt bit, which indicates the si3050 is communi cating with the si3019. ? off-hook : shows the status of the off-hook bit, daa register 5, bit 1. ? cir bits : allows writing and reading of cir bits. (gci only).
si3050-evb 10 rev. 1.1 figure 5. configure daa panel 5.5. advanced configuration advanced configuration of the application software is accomplished by using the ?configure daa? selection in the ?configure? menu. the configuration panel is shown in figure 5. the panel contents are detailed in the following list: ? fft window : the fft window applied to the time domain data before calculating the fft. ? acquisition buffer size : this is the size of the buffer, in samples, that is acquired and displayed on the line monitoring mode waveform graph. the buffer size can be set to between 1024 and 65536 samples in incremen ts of 512 samples. ? display measurement : takes realtime measurements of audio waveform.
si3050-evb rev. 1.1 11 figure 6. si3050 signal flow diagram 5.6. signal flow diagrams the signal flow diagrams of the application software shown in figure 6 on page 11 and figure 7 on page 12 assist users with programming daa. 5.7. si3050 signal path control ? pcml: turns on/off the pcml bit on daa register 33, bit 7 ? tx mute: turns on/off the txm bit on daa register 15, bit 7 ? tx gain: writes to tga2, txg2, tga3, and txg3 on daa register 38 and 40 ? iire: turns on/off iire bit on register 16, bit 4 ? ddl: turns on/off ddl bit on register 10, bit 1 ? rx mute: turns on/off rxm bit on register 15, bit 0 ? rx gain: writes to rga2, rxg2, rga3, and rxg3 on daa register 39 and 41 ? filt: turns on/off filt bit on register 31, bit 1 ? arm: writes to arm on register 20 ? atm: writes to atm on register 21 ? inte: turns on/off inte bit on register 2, bit 7 ? intp: turns on/off intp bit on register 2, bit 6 ? aout: writes to pwmm and pwem on register 1 si3019 signal path control
si3050-evb 12 rev. 1.1 figure 7. si3019 signal flow diagram 5.8. si3019 signal path control ? al: turns on/off al bit on register 2, bit 3 ? hbe: turns on/off hbe bit on register 2, bit 1 ? rxe: turns on/off rxe bit on register 2, bit 0 ? idl: turns on/off idl bit on register 1, bit 1 ? pdl: turns on/off pdl bit on register 6, bit 4 ? full: turns on/off full bit on register 31, bit 7
si3050-evb rev. 1.1 13 figure 8. transhybrid loss 5.9. transhybrid loss calculation when ?transhybrid loss calc ulation? is selected, the si3050ppt-evb software will drive a signal with different frequencies and measure the transhybrid loss based on the following equation: tl = 20log(txpk-pk/ rxpk-pk). frequencies used to measure this start from100 hz to 4000 hz in 20 hz steps.
si3050-evb 14 rev. 1.1 figure 9. ringing 5.10. ringing ? rngv-enable: turns on/off rngv bit on register 24, bit7 ? ras[5:0]: update ras bits on register 24 ? rmx[5:0]: update rmx bits on register 22 ? rcc[2:0]: update rcc bits on register 23 ? rto[3:0]: update rto bits on register 23 ? rdly[2:0]: update rdly bi ts on register 22 & 23 ? fmin(hz): calculate fmin based on ras bits ? fmin(hz): calculate fmax based on ras bits and rmx bits ? ring confirmation count (ms): shows ring confirmation count based on rcc bits ? ring timeout(ms): displays ring timeout based on rto bits ? ring delay(ms): displays ri ng delay based on rdly bits
si3050-evb rev. 1.1 15 d ocument c hange l ist revision 0.2 to revision 0.3 ? updated schematics ? updated boms ? updated layers revision 0.3 to revision 0.4 ? "1. functional description" on page 2: deleted text ? table 3 moved ? figure 4 updated ? figure 8 updated ? "5.8. si3019 signal path control" on page 12: added text. ? "5.9. transhybrid loss calculation" on page 13 added. revision 0.4 to revision 1.0 ? updated si3050 evb schematics. ? updated si3050 evb layout. ? updated si3050 evb bom. ? added notification of support for windows xp. ? updated layout figure titles. revision 1.0 to revision 1.1 ? updated to include si3050ppt1-evb and SI3050FMPPT-EVB as well as si3050ppt-evb ? removed schematics, bom, and layout sections; these are included on the disk supplied with the evaluation boards.
si3050-evb 16 rev. 1.1 c ontact i nformation silicon laboratories inc. 400 west cesar chavez austin, tx 78701 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 please visit the silicon labs technical support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. si-link, silicon laboratories, and silicon labs are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believed to be accurate in all respects at the time of publ ication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and om issions, and disclaims responsibi lity for any consequences resu lting from the use of information included herein. ad ditionally, silicon laboratorie s assumes no responsibility for the functioning of und escribed features or parameters. silicon laboratories reserves the right to make changes without further notice . silicon laboratories makes no wa rranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laboratories as sume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including wi thout limitation conse- quential or incidental damages. silicon laborat ories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of t he silicon laboratories product could create a s ituation where per- sonal injury or death may occur. should buyer purchase or us e silicon laboratories products for any such unintended or unauthor ized ap- plication, buyer shall indemnify and hold silicon laboratories harmles s against all claims and damages.

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